Sensor Circuit for Concurrent Integration of Multiple Differential Signals and Operating Method Thereof

ABSTRACT

The present invention provides a circuit for concurrent integration of multiple differential signals. The circuit comprises a plurality of Stage 1 integration circuit arranged in array and a plurality of Stage 2 integration circuit arrange in array. Each of said Stage 1 integration circuit is configured to concurrently integrate an input signal to send out a Stage 1 positive signal and a Stage 1 negative signal which is reverse to said Stage 1 positive signal. Each of said Stage 2 integration circuit is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to said corresponding Stage 1 integration circuit to output a Stage 2 signal.

CROSS REFERENCE TO RELATED PATENT APPLICATION

This patent application claims the domestic priority of the U.S.provisional application 61/564,995 filed on Nov. 30, 2011 and of theU.S. application Ser. Nos. 13/609,377 filed on Sep. 11, 2012 and13/609,524 filed on Sep. 11, 2012, and hereby incorporated byreferences.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a sensor circuit module,especially to a multi-stage sensor circuit module.

2. Description of the Prior Art

A sample and hold circuit for a traditional touch panel may be saturateddue to large instantaneous noise. The instantaneous noise may come froma power supply, a conductive substance touching the panel, a human bodyapproaching the panel or the like, causing a difference between asensing value of a sensor in the touch panel and a value sampled andheld by the S/H circuit. In other words, the S/H circuit must discardthe value sampled and held this time, and then perform S/H operation onthe sensing value of the sensor in the touch panel again. As such, notonly the operation time for the S/H circuit is increased, and it may notbe possible to measure the original sensing value of the sensor in thetouch panel in the next S/H operation. (For example, assuming in theprevious S/H operation the S/H circuit has obtained 40% of the sensingvalue of the sensor in the touch panel, but this value is discarded dueto saturation caused by the instantaneous noise, then the S/H circuitmay only obtain the remaining 60% of the sensing value of the sensor inthe current S/H operation).

Moreover, the S/H circuits for traditional touch panels typicallyoperate only in the positive or negative pulses, so 50% of the clockcycles are wasted. Alternatively, some S/H circuits employ inverters sothat they can operate in both the positive and negative pulses (e.g.negative pulses are converted into positive pulses via the inverter, anda S/H circuit operating in the positive pulses can now operate in whatoriginally were the negative pulses). However, transmission time delaysin the inverters may result in pulse overlap in high-speed S/H circuits.For example, assuming that after a negative pulse is converted into apositive pulse via an inverter a 5% transmission time delay isintroduced to the pulse, then the pulse time of the last 5% of thewaveform of this positive pulse will overlap the pulse time of the first5% of the waveform of the next positive pulse. This pulse overlapproblem is more noticeable and severe particularly in high-frequency S/Hcircuits or inverters with large transmission time delays, which mayeven result in S/H circuit disorder. Alternatively, some S/H circuitsemploy inverters to directly perform phase conversion on the resultssampled and held by the S/H circuits before using them. However, controlclocks of the inverters and the transmission time delays are stillproblems that are yet to be solved.

In view of these shortcomings, the present invention thus provides amulti-stage S/H circuit for positive and negative pulse cycles thatalleviates the saturation issue caused by the instantaneous noise in thetraditional S/H circuits and addresses the pulse overlap problem in thetraditional S/H circuits for positive and negative pulse cycles, whileachieving S/H operations for positive and negative pulse cycles.

Among traditional ADC, SAR-ADC is one of common ADC. In the design ofSAR-ADC, a binary tree structure is formed by a capacitor array.Utilizing a comparator and a control logic, the SAR-ADC can deliver anoutput bits which has nth order of 2. As mentioned above, ordinary S/Hcircuit also comprises capacitor used to integrate the input analogsignal.

Since the capacitor occupies quite large die area, if capacitors can beshared by S/H circuit and the attached SAR-ADC, some die area could bespared for decreasing manufacture cost.

SUMMARY OF INVENTION

The present invention provides a circuit for concurrent integration ofmultiple differential signals. The circuit comprises a plurality ofStage 1 integration circuit arranged in array and a plurality of Stage 2integration circuit arrange in array. Each of said Stage 1 integrationcircuit is configured to concurrently integrate an input signal to sendout a Stage 1 positive signal and a Stage 1 negative signal which isreverse to said Stage 1 positive signal. Each of said Stage 2integration circuit is configured to integrate a differential signalfrom a Stage 1 positive signal sent from a corresponding Stage 1integration circuit and a Stage 1 negative signal sent from anotherStage 1 integration circuit next to said corresponding Stage 1integration circuit to output a Stage 2 signal.

In one embodiment of the present invention, a sensor circuit module isprovided. The sensor circuit module comprises a first Stage 1 sample andhold (S/H) circuit, a second Stage 1 S/H circuit, and a first Stage 2S/H circuit. The first Stage 1 sample and hold (S/H) circuit isconfigured to integrate a first input signal and to send out a firstpositive signal and a first negative signal. The first positive signalis reverse to said first negative signal. The second Stage 1 S/H circuitis configured to integrate a second input signal and to send out asecond positive signal and a second negative signal. The second positivesignal is reverse to said second negative signal. The first Stage 2 S/Hcircuit is configured to receive and combine said first positive signaland said second negative signal into a first Stage 2 input signal to beintegrated by said first Stage 2 S/H circuit.

In another embodiment of the present invention, an operating method of asensor circuit module is provided. The operating method comprises:receiving a first positive signal from a first Stage 1 S/H circuit;receiving a second negative signal from a second Stage 1 S/H circuit;receiving and combining said first positive signal and said secondnegative signal to a first Stage 2 input signal; and integrating saidfirst Stage 2 input signal. The first positive signal is reverse to afirst negative signal from said first Stage 1 S/H circuit. The secondnegative signal is reverse to a second positive signal from said secondStage 1 S/H circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram shows a multi-stage sample and hold circuit inaccordance with an embodiment of the present invention.

FIG. 1B is a diagram shows another multi-stage sample and hold circuitin accordance with an embodiment of the present invention.

FIG. 2 is a diagram illustrates components of a sensor circuit module inaccordance with an embodiment of the present invention.

FIG. 3A is a diagram illustrates components of another sensor circuitmodule in accordance with an embodiment of the present invention.

FIG. 3B is a waveform diagram of the sensor circuit module shown in theFIG. 3A.

FIG. 3C is a diagram illustrates components of another sensor circuitmodule in accordance with an embodiment of the present invention.

FIG. 3D is a waveform diagram of the sensor circuit module shown in theFIG. 3C.

FIG. 3E is a diagram illustrates components of another sensor circuitmodule in accordance with an embodiment of the present invention.

FIG. 4 is a diagram depicts an amplifier shown in the FIG. 2.

FIG. 5A is a diagram depicts a successive approximation register analogto digital converter (SAR-ADC) in accordance with an embodiment of thepresent invention.

FIG. 5B is a diagram shows components of the SAR-ADC shown in the FIG.5A.

FIG. 5C is a waveform diagram of the SAR-ADC shown in the FIG. 5A.

FIG. 5D is a diagram depicts another successive approximation registeranalog to digital converter (SAR-ADC) in accordance with an embodimentof the present invention.

FIG. 5E is a diagram shows components of the SAR-ADC shown in the FIG.5D.

FIG. 5F is a waveform diagram of the SAR-ADC shown in the FIG. 5D.

FIG. 5G is a diagram illustrates an input signal switch in accordancewith an embodiment of the present invention.

FIG. 6A is a flow chart diagram illustrates an operating method of ananalog to digital converter in accordance with an embodiment of thepresent invention.

FIG. 6B is a flow chart diagram illustrates an operating method of ananalog to digital converter in accordance with another embodiment of thepresent invention.

FIG. 6C is a flow chart diagram illustrates an operating method of ananalog to digital converter in accordance with another embodiment of thepresent invention.

FIG. 7A is a flow chart diagram illustrates an operating method of ananalog to digital converter in accordance with an embodiment of thepresent invention.

FIG. 7B is a flow chart diagram illustrates an operating method of ananalog to digital converter in accordance with another embodiment of thepresent invention.

FIG. 7C is a flow chart diagram illustrates an operating method of ananalog to digital converter in accordance with another embodiment of thepresent invention.

FIG. 7D is a timing sequence diagram depicts an operating method of ananalog to digital converter in accordance with another embodiment of thepresent invention.

FIG. 8A is a block diagram shows a sensor circuit module in accordancewith the present invention.

FIG. 8B is a block diagram shows another sensor circuit module inaccordance with the present invention.

FIG. 8C is a block diagram shows another sensor circuit module inaccordance with the present invention.

FIG. 9A is a flow chart diagram depicts an operating method of a sensorcircuit module in accordance with the present invention.

FIG. 9B is a flow chart diagram depicts an operating method of a sensorcircuit module in accordance with the present invention.

FIG. 9C is a flow chart diagram depicts an operating method of a sensorcircuit module in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Some embodiments of the present invention are described in detailsbelow. However, in addition to the descriptions given below, the presentinvention can be applicable to other embodiments, and the scope of thepresent invention is not limited by such, rather by the scope of theclaims. Moreover, for better understanding and clarity of thedescription, some components in the drawings may not necessary be drawnto scale, in which some may be exaggerated relative to others, andirrelevant parts are omitted.

Referring to FIG. 1A, a block diagram illustrating a preferredembodiment 10 of the present invention is shown. A first sample and hold(S/H) circuit 110 samples a sensing signal of a sensor in multiplestages and accumulates them into a first sampled signal, and outputsthis first sampled signal at a first determined time. A second S/Hcircuit 120 receives a plurality of the first sampled signals outputtedby the first S/H circuit 110 and sums them into a second sampled signal,and outputs this second sampled signal at a second determined time. Inthis embodiment, the first S/H circuit 110 first samples the sensingsignal of the sensor in multiple short durations, and then accumulatesthem and stores it, and then outputs it to the second S/H circuit 120.The second S/H circuit 120 receives a plurality of outputs from thefirst S/H circuit 110 and sums them and stores it, and finally outputsthe total sensing signal of the sampled sensor.

In the operations of the first S/H circuit 110 and the second S/Hcircuit 120, although the first S/H circuit 110 may be saturated due tothe instantaneous noise being too large, this only affects a smallportion of the multi-sampled results of the first S/H circuit 110, andthe sampled results of the second S/H circuit 120 will not besignificantly influenced, thus eliminating the saturation issue of thetraditional S/H circuits as a result of the instantaneous noise beingtoo large. For example, assuming the first S/H circuit 110 samples andaccumulates the sensing signal in three short durations (e.g. 3times/0.5 pulse) before outputting it to the second S/H circuit 120; andthe second S/H circuit 120 receives and sums 20 outputs of the first S/Hcircuit 110 before outputting the total sensing signal sampled, theneven if the first S/H circuit 110 is saturated one or a few times due tothe instantaneous noise, it would be more difficult to saturate thesecond S/H circuit 120 during the sampling process, thereby increasingthe tolerance to noise of the S/H circuit. Furthermore, for the totalsampled sensing signal, even if one or some saturated result(s) of thefirst S/H circuit 110 is discarded, the effect on the total sampledsensing signal is relatively smaller than that in the prior art. Forexample, assuming two sampled results of the first S/H circuit 110 havebecome saturated due to the instantaneous noise being too large, butthese two is only 1/10 of the total 20.

Referring to FIG. 1B, a block diagram illustrating a preferredembodiment 15 of the present invention is shown. Functions andcorresponding relationships of two first S/H circuits 160A and 160B andtwo second S/H circuits 170A and 170B are similar to those of the firstS/H circuit 110 and the second S/H circuit 120 described in FIG. 1A. Thedifference is in that the two first S/H circuits 160A and 160B furtherprovide sampled results with polarities opposite to those of theoriginal to specific second S/H circuits. In this embodiment, forexample, the first S/H circuit 160B further outputs sampled results withinverted polarities to the second S/H circuit 170A, thereby eliminatingthe noise in the sensing signals. The following will be described usingthis embodiment, and one with ordinary skill in the art can make variousmodifications based on the descriptions of this embodiment withoutdeparting from the scope of the present invention, and thus thesemodifications will not be described in the application.

Referring still to FIG. 1B, the first S/H circuits 160A and 160B eachsamples a respective sensing signal of two sensors A and B in multipleshort durations and accumulate them into two first sampled signals, andthen outputs the two positive and negative first sampled signals in afirst determined time. In this embodiment, the first S/H circuits 160Aand 160B each outputs the positive first sampled signal to therespective second S/H circuits 170A and 170B; meanwhile, the first S/Hcircuit 160A also outputs the negative first sampled signal to anothersecond S/H circuit; the first S/H circuit 160B also outputs the negativefirst sampled signal to the second S/H circuit 170A; and the second S/Hcircuit 170B also receives the negative first sampled signal of anotherfirst S/H circuit at the same time. According to the above operations,the second S/H circuits 170A and 170B each receives the difference ofthe first sampled signals. Take the second S/H circuit 170A as anexample, it receives both the positive first sampled signal from thefirst S/H circuit 160A and the negative first sampled signal from thefirst S/H circuit 160B, when the adjacent sensors A and B bothexperience similar noise, the noise in the positive and negative firstsampled signals will cancel each other out, that is, this difference isa sampled sensing value with low noise. Since during the actual sensingof a typical touch panel, adjacent or nearby sensors often have the sameamount of sensing noise, so a large portion of such sensing noise can beeliminated through the above processing mechanism in this embodiment.Thus, in this embodiment, the sensors A and B can be two adjacent ornearby sensors in a touch panel.

The above description illustrates the operations of the embodiment shownin FIG. 1B in positive pulse cycles, the operations in negative pulsecycles are described as follow. The first S/H circuits 160A and 160Beach still samples the respective sensing signal of the two sensors Aand B in multiple short durations and accumulate them into two firstsampled signals, and then outputs the two positive and negative firstsampled signals in a first determined time. The difference is in that,in here, the first S/H circuits 160A and 160B each outputs the negativefirst sampled signal to the respective second S/H circuits 170A and170B; meanwhile, the first S/H circuit 160A also outputs the negativefirst sampled signal to another second S/H circuit; the first S/Hcircuit 160B also outputs the positive first sampled signal to thesecond S/H circuit 170A; and the second S/H circuit 170B also receivesthe positive first sampled signal of another first S/H circuit at thesame time. According to these operations, the second S/H circuits 170Aand 170B each also receives the difference of the first sampled signals.Again, take the second S/H circuit 170A as an example, it receives boththe negative first sampled signal from the first S/H circuit 160A andthe positive first sampled signal from the first S/H circuit 160B, andwhen the adjacent sensors A and B both experience similar noise, thenoise in the positive and negative first sampled signals will canceleach other out, that is, this difference is still a sampled sensingvalue with low noise. Based on the processes and descriptions above, thepresent embodiment can operate in both the negative and positive pulsecycles, and the concept of difference is used for eliminating the noise.In an example of the present invention, the second S/H circuits provideoutputs of the positive pulse cycles and outputs of the negative pulsecycles separately. In another example of the present invention, thesecond S/H circuits provide outputs of an accumulation of a positive anda negative pulse cycle. In yet another example of the present invention,the second S/H circuits provide outputs of an accumulation of multiplepositive and negative pulse cycles.

Referring to FIG. 2, a circuit diagram illustrating a preferred circuit20 combining the embodiments described with respect to FIGS. 1A and 1Bof the present invention is shown. A plurality of first S/H circuits 210sample corresponding plurality of sensing signals in multiple stages viaa plurality of paths (e.g. paths 0, 1, . . . 46 and 47), and thenaccumulates them into a plurality of first sampled signals, and outputsthe first sampled signals in a first determined time. A plurality ofsecond S/H circuits 230 correspondingly receive the first sampledsignals outputted multiple times by the first S/H circuits 210, and sumthem into a plurality of second sampled signals, and output the secondsampled signals at a second determined time. In this embodiment,according to the operation principle of the embodiment 10 described inFIG. 1A, even if one (or some) of the first S/H circuits 210 is (are)saturated due to the instantaneous noise being too large, this onlyaffects a small portion of the multi-stage sampled results of this(these) first S/H circuit(s) 210, and the sampled results of its (ortheir) corresponding second S/H circuit(s) 230 will not be greatlyinfluenced, thus lessening the saturation issue of the traditional S/Hcircuits as a result of the instantaneous noise being too large. Inaddition, in this embodiment, according to the operation principle ofthe embodiment 15 described in FIG. 1B, each first S/H circuit 210samples the sensing signal of a corresponding sensor in multiple shortdurations via the corresponding path; and each second S/H circuit 230receives both the positive first sampled signal (or the negative firstsampled signal) output from its corresponding first S/H circuit 210 andthe negative first sampled signal (or the positive first sampled signal)output from an adjacent first S/H circuit 210 at the same time. Thus,this embodiment not only operates in positive and negative pulse cycles,but also uses differences to eliminate the noise.

Referring still to FIG. 2, a plurality of (in this embodiment two)analog-to-digital (AD) converters 250 each receives the second sampledsignals outputted by a corresponding portion of the second S/H circuits230, and converts the received second sampled signals from analog todigital form using timing control. A plurality of (in this embodimenttwo) multiplexers 260 each receives the second sampled signals outputtedby a corresponding portion of the second S/H circuits 230, and selectsone of them. A plurality of (in this embodiment two) buffer amplifier270 each receives a corresponding output of the multiplexers 260 andperforms amplification, wherein the buffer amplifier 270 have aplurality of amplifying ratios to choose from.

Referring now to FIGS. 3A and 3B, a detailed circuit diagram and atiming diagram illustrating some portions of the first S/H circuits, thesecond S/H circuit and AD converters in the embodiment shown in FIG. 2are shown, respectively. Each first S/H circuit includes an operationalamplifier (e.g. a first operational amplifier 310A or 310B), twocapacitors (e.g. a first capacitor C1A or C1B and a second capacitor C2Aor C2B) and a plurality of switches (e.g. 311A, 312A, 313A, 314A, 315A,316A, 317A, 318A, 319A, 320A and 321A or 311B, 312B, 313B, 314B, 315B,316B, 317B, 318B, 319B, 320B and 321B), wherein the two capacitors areconnected in parallel and forming a first integration circuit with theoperational amplifier. The plurality of switches are connected to thecharge/discharge paths of the two capacitors, thereby controlling timeand polarity of charge/discharge of the two capacitors. Each second S/Hcircuit also includes an operational amplifier (e.g. a secondoperational amplifier 330A or 330B), a capacitor (e.g. a third capacitorC0 or C1) and a plurality of switches (e.g. 331A, 332A, 333A, 334A,335A, 336A, 337A and 338A or 331B, 332B, 333B, 334B, 335B, 336B, 337Band 338B), wherein the capacitor and the operational amplifier form asecond integration circuit, and the plurality of switches are connectedto signal input selecting paths and the charge/discharge paths of thecapacitor, thereby selecting an input signal and controllingcharge/discharge times of the capacitor.

Referring still to FIGS. 3A and 3B, when a timing signal k1 forcontrolling a plurality of first charge switches (e.g. first switches311A and 311B, second switches 312A and 312B, third switches 313A and313B and fourth switches 314A and 314B) is a positive pulse, sensingsignals on the path 0 and path 1 charge the first capacitors C1A and C1Band the second capacitors C2A and the C2B (as indicated by solid-linepaths), that is, the two first S/H circuits perform sampling on thesensing signals of the two corresponding sensors via the paths 0 and 1,respectively. When a timing signal k2 for controlling a plurality offirst discharge switches (e.g. fifth switches 315A and 315B, sixthswitches 316A and 316B, seventh switches 317A and 317B and eighthswitches 318A and 318B) is a positive pulse, the first capacitors C1Aand C1B and the second capacitors C2A and C2B discharge to the secondS/H circuits (as indicated by dotted-line paths), that is, the two firstS/H circuits output sampled and held results. In this embodiment, threek1 positive pulses are followed by 1 k2 positive pulse, in other words,the first S/H circuits in this embodiment performs 3 samplings in shortdurations, accumulates them and then outputs the result to the secondS/H circuits. The number of short-duration samplings for accumulationperformed by the first S/H circuits can be adjusted according to actualneeds, and the present invention is not limited to this. In addition,based on the discharge paths of the first capacitors C1A and C1B and thesecond capacitors C2A and C2B, the first S/H circuits in this embodimentoutputs both positive and negative sampled results to the second S/Hcircuit. For example, the first capacitor C1A outputs a positive sampledresult to the first selecting switch 331A via the sixth switch 316Ausing Vdd/2 as a reference potential; and the second capacitor C2Aoutputs a negative sampled result to the third selecting switch 333A viathe seventh switch 317A using Vdd/2 as a reference potential. Similarly,the first capacitor C1B outputs a positive sampled result to the firstselecting switch 331B via the sixth switch 316B using Vdd/2 as areference potential; and the second capacitor C2B outputs a negativesampled result to the third selecting switch 333B via the seventh switch317B using Vdd/2 as a reference potential, and the first capacitor C1Bfurther outputs the positive sampled result to the second selectingswitch 333A and the negative sampled result to the fourth selectingswitch 334A.

Referring again to FIGS. 3A and 3B, when a timing signal k0 b forcontrolling a plurality of clear switches (e.g. ninth switches 319A and319B and tenth switches 320A and 320B) is a positive pulse, the firstcapacitors C1A and C1B and the second capacitors C2A and C2B aredischarged and cleared. In this embodiment, a k0 b positive pulseappears before every three k1 positive pulses and after every k2positive pulse. This means that before the first S/H circuits performthe multi-stage samplings and accumulations, and after the first sampledsignals are outputted, the first capacitors C1A and C1B and the secondcapacitors C2A and C2B are cleared to ensure no residual charge willaffect the next sampled results. Sample control switches 321A and 321Bare controlled with the inversion of the timing signal k1, so that whenthe sample control switches 321A and 321B are conducting, the first S/Hcircuits, the first S/H circuits will be unable to perform samplings andaccumulations.

Referring again to FIGS. 3A and 3B, when timing signals k0 w 0 and k0 w1 for controlling second charge switches (e.g. eleventh switches 335Aand 335B and twelfth switches 336A and 336B) and a timing signal p1 forcontrolling the first selecting switches 331A and 331B and the fourthselecting switches 334A and 334B are positive pulses, then the positivesampled result from the first capacitor C1A and the negative sampledresult from the adjacent second capacitor C2B will simultaneously chargethe third capacitor C0. Similarly, the positive sampled result from thefirst capacitor C1B and the negative sampled result from anotheradjacent second capacitor will simultaneously charge the third capacitorC1. In other words, the two second S/H circuits each simultaneouslyreceives a positive first sampled signal outputted from itscorresponding first S/H circuit and a negative first sampled signaloutputted from its adjacent first S/H circuit. Since adjacent or nearbysensors in the touch panels often have similar sensing noise, so throughthe above process of obtaining the differences, the sensing noise in thepositive and negative first sampled signals will cancel out each other,that is, the two second S/H circuits will receive sampled sensing valueswith low noise.

Referring again to FIGS. 3A and 3B, when the timing signals k0 w 0 andk0 w 1 for controlling second charge switches (e.g. eleventh switches335A and 335B and twelfth switches 336A and 336B) and a timing signal p2for controlling the second selecting switches 332A and 332B and thethird selecting switches 333A and 333B are positive pulses, then thenegative sampled result from the second capacitor C2A and the positivesampled result from the adjacent first capacitor C1B will simultaneouslycharge the third capacitor C0. Similarly, the negative sampled resultfrom the second capacitor C2B and the positive sampled result fromanother adjacent first capacitor will simultaneously charge the thirdcapacitor C1. In other words, the two second S/H circuits eachsimultaneously receives a negative first sampled signal outputted fromits corresponding first S/H circuit and a positive first sampled signaloutputted from its adjacent first S/H circuit. Through this process ofobtaining the differences, the sensing noise in the positive andnegative first sampled signals will cancel out each other, that is, thetwo second S/H circuits will receive sampled sensing values with lownoise.

In this embodiment, the timing signal p1 and the timing signal p2 aresignals with the same frequency but 180 degrees out of phase. If thetiming signal p1 is regarded as the operating timing signal, then thepresent embodiment can operate in both the positive and negative pulsesof the timing signal p1. Furthermore, in this embodiment, after 10 μlcycles (20 half cycles), the timing signals k0 w 0 and k0 w 1 forcontrolling the second charge switches (e.g. eleventh switches 335A and335B and twelfth switches 336A and 336B) sequentially change frompositive to a low voltage potential, and timing signals k0 c 0 and k0 c1 for controlling second discharge switches (e.g. thirteenth switches335A and 335B and fourteenth switches 336A and 336B) sequentially changefrom a low voltage potential to positive, the third capacitors C0 and C1sequentially discharge to the AD converter 250 via the fourteenthswitches 336A and 336B using Vdd/2 as the reference potential, that is,the two second S/H circuit finishes sampling and sequentially output S/Dresults to the AD converter 250 for conversion.

Referring to FIGS. 3C and 3D, a circuit diagram and a timing diagram ofa preferred circuit according to the embodiment described in FIG. 1A areshown, respectively. Basically, the embodiment shown in FIG. 3Csimplifies some functions and elements of the embodiment shown in FIG.3A. The difference between the two is in that each first S/H circuit ofthe embodiment shown in FIG. 3C uses only one capacitor and the relevantcharge/discharge switches. That is, each first S/H circuit contains oneoperational amplifier (e.g. first operational amplifier 310A and 310B),a capacitor (e.g. a first capacitor C1A or C1B) and a plurality ofswitches (e.g. 311A, 312A, 315A, 316A, 319A and 321A or 311B, 312B,315B, 316B, 319B and 321B), wherein the capacitor and the operationalamplifier form a first integration circuit, and the plurality ofswitches correspond to the charge/discharge paths connected with thecapacitor, thereby controlling the charge/discharge times of thecapacitor. Also, each second S/H circuit does not contain the selectingswitches (e.g. 331A, 332A, 333A and 334A or 331B, 332B, 333B and 334B)in FIG. 3A, but instead is directly coupled to the output of thecorresponding first S/H circuit. That is, each second S/H circuitincludes an operational amplifier (e.g. a second operational amplifier330A or 330B), a capacitor (e.g. a third capacitor C0 or C1) and aplurality of switches (335A, 336A, 337A and 338A or 335B, 336B, 337B and338B), wherein the capacitor and the operational amplifier form a secondintegration circuit and the plurality of switches correspond to thecharge/discharge paths connected with the capacitor, thereby controllingcharge/discharge times of the capacitor.

Referring still to FIGS. 3C and 3D, when a timing signal k1 forcontrolling a plurality of first charge switches (e.g. first switches311A and 311B and second switches 312A and 312B) is a positive pulse,sensing signals on the path 0 and path 1 charge the first capacitors C1Aand C1B, that is, the two first S/H circuits perform sampling on thesensing signals of the two corresponding sensors via the paths 0 and 1,respectively. When a timing signal k2 for controlling a plurality offirst discharge switches (e.g. fifth switches 315A and 315B and sixthswitches 316A and 316B) is a positive pulse, the first capacitors C1Aand C1B discharge to the second S/H circuits, that is, the two first S/Hcircuits output sampled and held results. In this embodiment, three k1positive pulses are followed by 1 k2 positive pulse, in other words, thefirst S/H circuits in this embodiment performs 3 samplings in shortdurations, accumulates them and then outputs the result to the secondS/H circuits. The number of short-duration samplings for accumulationperformed by the first S/H circuits can be adjusted according to actualneeds, and the present invention is not limited to this. In contrast tothe embodiment of FIG. 3A, the first S/H circuits of this embodimentdoes not output both positive and negative sampled results at the sametime, that is, the two S/H circuits only output positive sampled resultsto corresponding second S/H circuits via the sixth switches 316A and316B by the two first capacitors C1A and C1B using Vdd/2 as thereference potential via the fifth switches 315A and 315B. As for theclear switches (e.g. ninth switches 319A and 319B) and its controltiming signal k0 b and sample control switches 321A and 321B and itscontrolling timing signal (inverted k1) are the same as those describedin FIGS. 3A and 3B, and will not be repeated.

Referring again to FIGS. 3C and 3D, when timing signals k0 w 0 and k0 w1 for controlling second charge switches (e.g. eleventh switches 335Aand 335B and twelfth switches 336A and 336B) are positive pulses, thenthe positive sampled result from the first capacitor C1A and C1B willcharge the third capacitor C0 and C1, respectively. In other words, thetwo second S/H circuits each receives a positive first sampled signaloutputted from its corresponding first S/H circuit. Unlike theembodiment shown in FIG. 3A, the second S/H circuits of the presentembodiment only receives positive first sampled signals of thecorresponding first S/H circuits, and thus this embodiment is notcapable of eliminating the noise using the differences as above, but iscapable of reducing saturation as a result of the instantaneous noisebeing too large. As for the operations of discharging the thirdcapacitors C0 and C1 to an AD converter 250 and of the relevant switches(e.g. eleventh switches 335A and 335B, twelfth switches 336A and 336B,thirteenth switches 337A and 337B, fourteenth switches 338A and 338B)and timing signals (e.g. k0 w 0, k0 w 1, k0 c 0 and k0 c 1) are the sameas those described in FIGS. 3A and 3B, and will not be repeated.

Referring to FIGS. 3E and 3D, a modified circuit and a timing diagram ofthe embodiment described in FIG. 3C are shown. In principle, theembodiment shown in FIG. 3E adds the function of eliminating the noiseby differences to the embodiment shown in FIG. 3C. The two embodimentsare different in that the first S/H circuits of the embodiment of FIG.3E does not output first sampled signals with always the same polarity,but providing first sampled signals with opposite polarities. Take thepaths 0 and 1 as an example, the first S/H circuit includes anoperational amplifier (e.g. a first operational amplifier 310A or 310B),a capacitor (e.g. a first capacitor C1A or a second capacitor C2B) and aplurality of switches (e.g. 311A, 312A, 315A, 316A, 319A, and 313B,314B, 317B, 318B, 319B and 321B), wherein the capacitor and theoperational amplifier form a first integration circuit and the pluralityof switches correspond to charge/discharge paths connected with thecapacitor, thereby controlling the charge/discharge times of thecapacitor. Also, the second S/H circuits not only receive the outputfrom the corresponding first S/H circuits, but also receive an output ofthe opposite polarity from a first S/H circuit on an adjacent path, andeach second S/H circuit includes an operational amplifier (e.g. a secondoperational amplifier 330A or 330B), a capacitor (e.g. a third capacitorC0 or C1) and a plurality of switches (e.g. 335A, 336A, 337A and 338A or335B, 336B, 337B and 338B), wherein the capacitor and the operationalamplifier form a second integration circuit, and the plurality ofswitches are connected to charge/discharge paths connected with thecapacitor, thereby controlling charge/discharge times of the capacitor.

Referring still to FIGS. 3E and 3D, when a timing signal k1 forcontrolling a plurality of first charge switches (e.g. a first switch311A, a second switch 312A, a third switch 313A and a fourth switch314A) is a positive pulse, sensing signals on the path 0 and path 1charge the first capacitor C1A and the second capacitor C2B,respectively. That is, the two first S/H circuits perform sampling onthe sensing signals of the two corresponding sensors via the paths 0 and1, respectively. When a timing signal k2 for controlling a plurality offirst discharge switches (e.g. a fifth switch 315A, a sixth switch 316A,a seventh switch 317B and an eighth switch 318B) is a positive pulse,the first capacitor C1A and the second capacitor C2B discharge to thesecond S/H circuits, that is, the two first S/H circuits output sampledand held results. In this embodiment, three k1 positive pulses arefollowed by 1 k2 positive pulse, in other words, the first S/H circuitsin this embodiment performs 3 samplings in short durations, accumulatesthem and then outputs the result to the second S/H circuits. The numberof short-duration samplings for accumulation performed by the first S/Hcircuits can be adjusted according to actual needs, and the presentinvention is not limited to this. In contrast to the embodiment of FIG.3C, adjacent first S/H circuit outputs a sampled result with an oppositepolarity, that is, the first capacitor C1A outputs a positive sampledresult to the corresponding second S/H circuit via the sixth switch 316Ausing Vdd/2 as the reference potential via the fifth switch 315A, andthe second capacitor C2B outputs a negative sampled result to thecorresponding second S/H circuit via the seventh switch 317B using Vdd/2as the reference potential via the eighth switch 318B. As for the clearswitches (e.g. a ninth switch 319A and 319B) and its control timingsignal k0 b and sample control switches 321A and 321B and itscontrolling timing signal (inverted k1) are the same as those describedin FIGS. 3A and 3B, and will not be repeated.

Referring again to FIGS. 3E and 3D, when timing signals k0 w 0 and k0 w1 for controlling second charge switches (e.g. eleventh switches 335Aand 335B and twelfth switches 336A and 336B) are positive pulses, thenthe positive sampled result from the first capacitor C1A and thenegative sampled result from the second capacitor C2B on the adjacentpath will simultaneously charge the third capacitor C0. Similarly, thenegative sampled result from the second capacitor C2B and a positivesampled result from a first capacitor on another adjacent path willsimultaneously charge the third capacitor C10. In other words, the twosecond S/H circuits each receives a positive (a negative) first sampledsignal outputted from its corresponding first S/H circuit and also anegative (a positive) first sampled signal outputted from the first S/Hcircuit on the adjacent path. Since adjacent or nearby sensors in thetouch panels often have similar sensing noise, so through the aboveprocess of obtaining the differences, the sensing noise in the positiveand negative first sampled signals will cancel out each other, that is,the two second S/H circuits will receive sampled sensing values with lownoise. Based on the above, this embodiment not only eliminates thesensing noise by the method of differences, but also reduces saturationresulting from the instantaneous noise being too large. As for theoperations of discharging the third capacitors C0 and C1 to an ADconverter 250 and of the relevant switches (e.g. eleventh switches 335Aand 335B, twelfth switches 336A and 336B, thirteenth switches 337A and337B, fourteenth switches 338A and 338B) and timing signals (e.g. k0 w0, k0 w 1, k0 c 0 and k0 c 1) are the same as those described in FIGS.3A and 3B, and will not be repeated. It should be noted that in thisembodiment the first sampled signals are provided with oppositepolarities, although this can eliminate noise by obtaining thedifferences, but the result output by the second S/H circuits will alsoexhibit opposite polarities. This can be corrected by using an inverter,which is well known to one with ordinary skill in the art, and will notbe further discussed.

Referring to FIG. 4, a circuit diagram illustrating a preferred circuitof the buffer amplifier 270 described with respect to FIG. 2 is shown. Aplurality of multiplying resistors R2, R3 and R4 are connected withrespective multiplying switches kg2, kg3 and kg4 in series, and areconnected in parallel with each other as well as another multiplyingswitch kg1, these then form a non-inverting amplifier circuit structurewith a third operational amplifier 410, a reference resistor R1 and areference switch ˜kg1. When the multiplying switch kg1 is shorted andthe reference switch ˜kg1 and the rest of the multiplying resistors kg2to kg4 are opened, the amplifying ratio of the third operationalamplifier 410 is 1. When the multiplying switch kg2 and the referenceswitch ˜kg1 are shorted while the rest of the multiplying resistors areopened, the amplifying ratio of the third operational amplifier 410 is(R1+R2)/R1. Similarly, it can be derived that the third operationalamplifier 410 may also have amplifying ratios of (R1+R3)/R1 and(R1+R4)/R1, so by replacing the feedback circuit with differentresistances, different amplifying ratios can be achieved.

Referring to FIGS. 5A and 5C, a block diagram and a timing diagram for apreferred sampling and conversion embodiment combining the second S/Hcircuits 230 and the AD converter 250 described with respect to FIG. 2are shown, respectively. An operational amplifier 510 and a capacitorarray 520 form a third integration circuit (corresponding to the secondS/H circuits 230 in FIG. 2), and a voltage VCM is used as the referencevoltage. The capacitor array 520 and a comparator 530 and a successiveapproximation register (SAR) control logic 540 form a SAR AD converter(SAR-ADC) (corresponding to the AD converter 250 in FIG. 2), and iscontrolled by a plurality of controlling signals (e.g. RST, INT andCMP). When the first control signal RST is positive, all the capacitorsin the capacitor array 520 will be reset (i.e. charges in the capacitorswill resume default values, typically zero, but not limited to this).When a second control signal INT is at a high potential, the thirdintegration circuit formed by the operational amplifier 510 and thecapacitor array 520 performs integration, that is, performs S/Hoperations (e.g. in FIG. 2, the second S/H circuits 230 sample the firstS/H circuits 210). When a third control signal CMP is high, the SAR-ADCformed by the capacitor array 520, the comparator 530 and the SARcontrol logic 540 performs successive approximation analog-to-digitalconversion on the results sampled and held by the capacitor array 520,thereby converting the S/H results from analog to digital form, whereinthe SAR control logic 540 further provides two output control signals542 and 544 for controlling outputs as ascending output (output from LSBto MSB) or descending output (output from MSB to LSB).

Referring to FIG. 5B, a circuit diagram illustrating a preferred circuitof FIG. 5A is shown. The operational amplifier 510 and the capacitorarray 520 including a plurality of capacitors 520C connected in parallelform the third integration circuit, and the voltage VCM is used as thereference voltage of the operational amplifier 510, wherein the firstend of each capacitor 520C is electrically coupled to three controlswitches (e.g. 522, 524 and 526), which are a first control switch 522that can be electrically coupled to the reference voltage VCM under thecontrol of the first control signal RST; a second control switch 524that can be electrically coupled to the input under the control of thesecond control signal INT; and a third control switch 526 that can beelectrically coupled to the input of the comparator 530 under thecontrol of the third control signal CMP, respectively. A second end ofeach capacitor 520C can be serially connected to a plurality of parallelswitches a, b, c and d to selectively and electrically couple with theoutput end of the operational amplifier 510 and a plurality of referencevoltages (e.g. VCM, VREFN and VREFP). The capacitor array 520, thecomparator 530 and the SAR control logic 540 form the SAR-ADC and areunder the control of the control signals RST, INT and CMP.

Referring to FIGS. 5B and 5C, when the first control signal RSTcontrolling the first control switch 522 and the plurality of switches bis positive, then the first control switch 522 and the plurality ofswitches b are turned on, so both ends of all of the capacitors 520C inthe capacitor array 520 are connected to the reference voltage VCM, thatis, charges inside all of the capacitors 520C will be reset to thedefault value (typically zero, but not limited to this). When the secondcontrol signal INT controlling the second control switch 524 and theplurality of switches a is at a high potential, then the second controlswitch 524 and the plurality of switches a are turned on, so theoperational amplifier 510 and all the capacitors in the capacitor array520 form the third integration circuit (corresponding to the second S/Hcircuits 230 in FIG. 2) and perform integration operations, that is,perform S/H operations on the input (corresponding to the second S/Hcircuits 230 sampling the first S/H circuits 210 in FIG. 2). When thethird control signal CMP is at a high potential, the third controlswitch 526 is turned on, and the SAR-ADC formed by the capacitor array520, the comparator 530 and the SAR control logic 540 performssuccessive approximation analog-to-digital conversion on the resultssampled and held by the capacitor array 520, thereby converting the dataform of the output, wherein the SAR control logic 540 provides twooutput control signals 542 and 544 for respectively controlling aplurality of switches c so that the reference voltage VREFN becomes theconversion reference voltage and controlling a plurality of switches dso that the reference voltage VREFP becomes the conversion referencevoltage, resulting in an descending output (output from MSB to LSB) andan ascending output (output from LSB to MSB) respectively.

Referring to FIGS. 5D and 5F, a block diagram and a timing diagram for amodified circuit of the embodiment in FIG. 5A are shown, respectively.Basically, the embodiment in FIG. 5D achieves the operations of theembodiment in FIG. 5A by a time-division pipelining manner. The twoembodiments are different in that the embodiment in FIG. 5D further addsanother capacitor array and the relevant control signals. That is, anoperational amplifier 510 and two capacitor array 520A and 520B form athird integration circuit at different times, and a voltage VCM is usedas the reference voltage. Said different times are controlled bycontrolling signals and control switches, so that the operationalamplifier 510 forms the third integration circuit with the only one ofthe capacitor arrays 520A and 520B at any one time. The capacitor arrays520A and 520B also form a SAR-ADC with a comparator 530 and a SARcontrol logic 540 at different times, and are controlled by a pluralityof control signals (e.g. RST1, INT1, CMP1 and RST2, INT2, CMP2).Similarly, said different times are controlled by controlling signalsand control switches, so that only one of the capacitor arrays 520A and520B forms the SAR-ADC with the comparator 530 and the SAR control logic540 at any one time. Based on the above, in this embodiment, when thecapacitor array 520A forms the third integration circuit with theoperational amplifier 510 for performing integration operations, thecapacitor array 520B forms the SAR-ADC with the comparator 530 and theSAR control logic 540 for performing AD conversion. Whereas when thecapacitor array 520B forms the third integration circuit with theoperational amplifier 510 for performing integration operations, thecapacitor array 520A forms the SAR-ADC with the comparator 530 and theSAR control logic 540 for performing AD conversion. Thus, when a firstcontrol signal RST1 is positive, then all the capacitors in thecapacitor array 520A will be reset (charges inside all of the capacitorswill resume the default value, typically zero, but not limited to this).Then, when a second control signal INT1 is at a high potential, then thecapacitor array 520A and the operational amplifier 510 form the thirdintegration circuit and perform integration operations, that is, performS/H operations on the input, meanwhile, a sixth control signal CMP2 isat a high potential, so the SAR-ADC formed by the capacitor array 520B,the comparator 530 and the SAR control logic 540 performs successiveapproximation analog-to-digital conversion on the results sampled andheld by the capacitor array 520B. Then, when a fourth control signalRST2 is positive, all the capacitors in the capacitor array 520B will bereset (charges inside all of the capacitors will resume the defaultvalue, typically zero, but not limited to this), and then when a thirdcontrol signal CMP1 is at a high potential, the SAR-ADC formed by thecapacitor array 520A, the comparator 530 and the SAR control logic 540performs successive approximation analog-to-digital conversion on theresults sampled and held by the capacitor array 520A. Meanwhile, a fifthcontrol signal INT2 is at a high potential, so the capacitor array 520Band the operational amplifier 510 form the third integration circuit andperform integration operations, that is, perform S/H operations on theinput. By repeating the above processes of the control signals, thisembodiment can be realized in a time-division pipelining manner, whichspeeds up the sampling and conversion processes. In addition, the SARcontrol logic 540 further provides two output control signals 546 and548 for controlling the converted outputs of the capacitor array 520Aand 520B to be descending output (output from MSB to LSB) or ascendingoutput (output from LSB to MSB).

Referring to FIG. 5E, a circuit diagram illustrating a preferred circuitof FIG. 5D is shown. The operational amplifier 510 and the capacitorarray 520A including a plurality of capacitors 520C₁ connected inparallel form the third integration circuit, and the voltage VCM is usedas the reference voltage of the operational amplifier 510, wherein thefirst end of each capacitor 520C₁ is electrically coupled to threecontrol switches (e.g. 522A, 524A and 526A), which are a first controlswitch 522A that can be electrically coupled to the reference voltageVCM under the control of the first control signal RST1; a second controlswitch 524A that can be electrically coupled to the input under thecontrol of the second control signal INT1; and a third control switch526A that can be electrically coupled to the input of the comparator 530under the control of the third control signal CMP1, respectively. Asecond end of each capacitor 520C₁ can be serially connected to aplurality of parallel switches a₁, b₁, c₁ and d₁ to selectively andelectrically couple with the output end of the operational amplifier 510and a plurality of reference voltages (e.g. VCM, VREFN and VREFP). Inaddition, the capacitor array 520A, the comparator 530 and the SARcontrol logic 540 form the SAR-ADC and are under the control of thecontrol signals RST1, INT1 and CMP1. The operational amplifier 510 andthe capacitor array 520B including a plurality of capacitors 520C₂connected in parallel also form the third integration circuit, and thevoltage VCM is used as the reference voltage of the operationalamplifier 510, wherein the first end of each capacitor 520C₂ iselectrically coupled to three control switches (e.g. 522B, 524B and526B), which are a fourth control switch 522B that can be electricallycoupled to the reference voltage VCM under the control of the fourthcontrol signal RST2; a fifth control switch 524B that can beelectrically coupled to the input under the control of the fifth controlsignal INT2; and a sixth control switch 526B that can be electricallycoupled to the input of the comparator 530 under the control of thesixth control signal CMP2, respectively. A second end of each capacitor520C₂ can be serially connected to a plurality of parallel switches a₂,b₂, c₂ and d₂ to selectively and electrically couple with the output endof the operational amplifier 510 and a plurality of reference voltages(e.g. VCM, VREFN and VREFP). In addition, the capacitor array 520B, thecomparator 530 and the SAR control logic 540 also form the SAR-ADC andare under the control of the control signals RST2, INT2 and CMP2.

Referring to FIGS. 5E and 5F, when the first control signal RST1controlling the first control switch 522A and the plurality of switchesb₁ is positive, then the first control switch 522A and the plurality ofswitches b₁ are turned on, so both ends of all of the capacitors 520C₁in the capacitor array 520A are connected to the reference voltage VCM,that is, charges inside all of the capacitors 520C₁ will be reset to thedefault value (typically zero, but not limited to this). When the secondcontrol signal INT1 controlling the second control switch 524A and theplurality of switches a₁ is at a high potential, then the second controlswitch 524A and the plurality of switches a₁ are turned on, so theoperational amplifier 510 and all the capacitors in the capacitor array520A form the third integration circuit (corresponding to the second S/Hcircuits 230 in FIG. 2) and perform integration operations, that is,perform S/H operations on the input (corresponding to the second S/Hcircuits 230 sampling the first S/H circuits 210 in FIG. 2). Meanwhile,the sixth controlling signal CMP2 is also at a high potential, so thesixth control switch 526B is turned on, and the SAR-ADC formed by thecapacitor array 520B, the comparator 530 and the SAR control logic 540performs successive approximation analog-to-digital conversion on theresults sampled and held by the capacitor array 520B. Then, when thefourth control signal RST2 controlling the fourth control switches 522Band the plurality of switches b₂ is positive, the fourth controlswitches 522B and the plurality of switches b₂ are turned on, and allthe capacitors 520C₂ in the capacitor array 520B are connected to thereference voltage VCM, that is, charges inside all of the capacitors520C₂ will resume the default value (typically zero, but not limited tothis). Thereafter, when the third control signal CMP1 is at a highpotential, the third control switch 526A is turned on, and the SAR-ADCformed by the capacitor array 520A, the comparator 530 and the SARcontrol logic 540 performs successive approximation analog-to-digitalconversion on the results sampled and held by the capacitor array 520A.Meanwhile, the fifth control signal INT2 controlling the fifth controlswitches 524B and the plurality of switches a₂ is at a high potential,so the fifth control switches 524B and the plurality of switches a₂ areturned on, and thus all the capacitors 520C₂ in the capacitor array 520Band the operational amplifier 510 form the third integration circuit(corresponding to the second S/H circuits 230 in FIG. 2) and performintegration operations, that is, perform S/H operations on the input. Byrepeating the above processes of the control signals, the two capacitorarray 520A and 520B in this embodiment can time share the operationalamplifier 510, the comparator 530 and the SAR control logic 540, thusachieving time-division pipelining operations. In other words, when thecapacitor array 520A forms the third integration circuit with theoperational amplifier 510 for performing integration operations, thecapacitor array 520B forms the SAR-ADC with the comparator 530 and theSAR control logic 540 for performing AD conversion; whereas when thecapacitor array 520B forms the third integration circuit with theoperational amplifier 510 for performing integration operations, thecapacitor array 520A forms the SAR-ADC with the comparator 530 and theSAR control logic 540 for performing AD conversion, thereby increasingthe overall operational speed. In addition, the SAR control logic 540further provides output control signals 542, 546 and 544, 548 forrespectively controlling a plurality of switches c₁ and c₂ so that thereference voltage VREFN becomes the conversion reference voltage, andcontrolling a plurality of switches d₁ and d₂ so that the referencevoltage VREFP becomes the conversion reference voltage, resulting in andescending output (output from MSB to LSB) and an ascending output(output from LSB to MSB) respectively.

Finally, it should be noted that the present invention provides circuitsfor holding positive and negative sampled signals are provided using acombination of two capacitors and an operational amplifier, and theabove circuits are combined to sample and hold a plurality ofdifferences of a plurality of paths (a plurality of sensors (orconductive strips) in a touch panel) (e.g. sampled values of path 2minus sampled values of path 1, sampled values of path 3 minus sampledvalues of path 2, . . . , sampled values of path m minus sampled valuesof path m−1; or, sampled values of path 1 minus sampled values of path2, sampled values of path 2 minus sampled values of path 3, . . . ,sampled values of path m−1 minus sampled values of path m). Thisarchitecture is used for mutual capacitive detection, that is, sensorsin one of the horizontal and vertical directions are driven(sequentially driven), and at the same time, signals from all thesensors in the other of the horizontal and vertical directions arereceived (all at the same time or in several stages). When each sensoris driven, sensors in the other direction are then sampled. The S/Hcircuits proposed by the present invention are used for latching all thesignals, so that common mode noise with fixed frequencies coming fromthe display can then be removed by obtaining the differences of thesignals.

In addition, the timing for performing S/H by the first S/H circuits canfall on the times when the display emits no or very low noise. Theselection of the clock frequency can be made by testing with severalpredetermined frequencies, or combinations of different frequencies andtimings, so that an appropriate combination of the frequency and thetiming can be determined. The determination of whether frequency shouldbe selected or changed can be made once at the beginning or regularlyduring the operation.

Please refer to FIG. 5A to 5C. In one embodiment of the presentinvention, an integration and analog to digital conversion circuitsharing common capacitors is provided. The circuit comprises a capacitorarray module 520, an integration circuit, and an analog to digitalconversion (ADC) logic (530 and 540 collectively). The capacitor arraymodule 520 comprises a plurality of capacitors 520C. The integrationcircuit integrates an analog signal (INPUT shown in the FIG. 5A.) TheADC logic converts the output of the capacitor array module 520 to adigital signal (OUTPUT shown in the FIG. 5A.)

The integration circuit comprises an OP amplifier, which has a firstinput end, a second input end, and an output end. The first input end iscoupled to the analog signal. The second input end is coupled to areference signal (for example, a reference voltage VCM.) The first inputend and the output end of the OP amplifier are coupled in parallel toboth ends of each of capacitor 520C, respectively. In other words, atleast part of all capacitors 520C is used for integration. The two endsof those capacitors used for integration are coupled to the input endand the output end of the integration circuit in parallel, respectively.The integration circuit is configured to integrate the analog signalaccording to the reference signal.

The ADC logic further comprises a comparator 530. The ADC logic, inturn, controls each of the plurality of capacitors 520C configured forintegration to output of the comparator 530 for converting the outputsof the plurality of capacitors 520C to the digital signal. Theintegration circuit takes control of the capacitor array module 520 whenperforming integration and the ADC logic takes control of the capacitorarray module 520 when performing conversion. The performing integrationand the performing conversion are in turn.

Please refer to FIG. 5A to 5C. In one embodiment of the presentinvention, an analog to digital converter (ADC) is provided. The ADC isconfigured to integrate an input signal and to convert it to a digitaln-bit signal (OUTPUT shown in the FIG. 5A.) The ADC comprises acapacitor array module (520 shown in the FIG. 5A), an OP amplifier (520shown in the FIG. 5A), a comparator (530 shown in the FIG. 5A), and acontrol logic (540 shown in the FIG. 5A.) The capacitor array module 520is configured to receive said input signal and a reference voltage VCM.The capacitor array module comprises a plurality of capacitors (520Cshown in the FIG. 5B.) The OP amplifier is configured to receive saidinput signal and said reference voltage VCM. An output end of said OPamplifier is coupled to said capacitor array module. As shown in theFIG. 5B, first ends of said plurality of capacitors are coupled to saidinput signal, said reference voltage VCM, or an input end of saidcomparator. The control logic is configured to receive an output signalof said comparator and to send out said n-bit digital signal and acontrol signal (542 and 544 collectively shown in the FIG. 5A) to saidcapacitor array module.

The capacitor array module further receives a reset signal RST. Secondends of said plurality of capacitors are coupled to a reset switch (522and switch b shown in the FIG. 5B) in parallel. When said reset signalRST is a first signal, said first end of said plurality of capacitorsare coupled to said reference voltage VCM and said reset switch isclosed. The first end and the second end of said capacitors areconnected to said reference voltage VCM.

The capacitor array module further receives an integration signal INT.Second ends of said plurality of capacitors are coupled to a integrationswitch (524 and switch a shown in the FIG. 5B) in parallel. Theintegration switch is connected to said output end of said OP amplifier.When said integration signal INT is a first signal, said first end ofsaid plurality of capacitors are coupled to said input signal inparallel and said integration switch is closed. The input signal isintegrated by said plurality of capacitors.

The capacitor array module further receives a comparison signal CMP.Second ends of each of said plurality of capacitors are coupled to afirst comparison switch and a second comparison switch (switch c andswitch d shown in the FIG. 5B.) The first comparison switch is connectedto a first reference voltage VREFN and the second comparison switch isconnected to a second voltage VREFP. Both the first and secondcomparison switches are controlled by said control signal. When thecomparison signal CMP is a first signal, said first ends of saidplurality of capacitors are coupled to said input end of said comparatorin parallel. Switch 526 shown in the FIG. 5B is closed. The controllogic receives said output of said comparators and to send out saidn-bit digital signal and said control signal to said capacitor arraymodule.

The number of said plurality of capacitors is n, and the capacity ratiobetween capacitors is 2's multiple.

Please refer to FIG. 5A to 5C and FIG. 6A to 6C. In one embodiment ofthe present invention, an operating method of an analog to digitalconverter is provided. The analog to digital converter comprises acapacitor array module, an OP amplifier, a comparator, and a controllogic. The capacitor array module is configured to receive an inputsignal and a reference voltage VCM. The capacitor array module comprisesa plurality of capacitors. First ends of said plurality of capacitorsare coupled to said input signal, said reference voltage VCM, or aninput end of said comparator. An output end of said comparator iscoupled to said capacitor array module. The said control logicconfigured to receive an output end of said comparator and send out ann-bit digital signal and a control signal to said capacitor arraymodule.

In one embodiment shown in the FIG. 6A, the operating method comprises:at step 610, coupling said first ends of said plurality of capacitors tosaid input signal in parallel; and at step 620, coupling second end ofsaid plurality of capacitors to an output end of said OP amplifier inparallel.

In another embodiment shown in the FIG. 6B, the operating methodcomprises: at step 630, coupling said first ends of said plurality ofcapacitors to said input end of said comparator in parallel; and at step640, coupling second ends of said plurality of capacitors to an outputend of said OP amplifier in parallel.

In one embodiment shown in the FIG. 6C, the operating method comprises:at step 650, coupling said first ends of said plurality of capacitors tosaid input end of said comparator in parallel; and at step 660,receiving an output end of said comparator by said logic and sending outsaid n-bit digital signal and a control signal to said capacitor module.

Second ends of each said plurality of capacitors are coupled to a firstcomparison switch and a second comparison switch. Said first comparisonswitch is connected to a first reference voltage VREFN and said secondcomparison switch is connected to a second reference voltage VRFP. Saidfirst and second comparison switches are controlled by said controlsignal. And the number of said plurality of capacitors is n. Thecapacity ratio between capacitors is 2's multiple.

Please refer to FIG. 5D to 5G. In one embodiment of the presentinvention, an integration and analog to digital conversion circuitsharing common capacitors is provided. The circuit comprises a firstcapacitor array module 520A, a second capacitor array module 520B, anintegration circuit, and an analog to digital conversion (ADC) logic.Both of the first and the second capacitor array modules 520A and 520Bcomprises a plurality of capacitors 520C₁ and 520C₂.

The integration circuit integrates an analog signal (INPUT shown in theFIG. 5D) by the first or the second capacitor array module. Theintegration circuit comprises an OP amplifier 510. The OP amplifier 510has a first input, a second input, and an output end. The first inputand the second input are connected to the analog signal and a referencesignal (for example, reference voltage VCM), respectively. The firstinput and the output end are coupled to both ends of each of capacitors520C₁ and 520C₂ configured to be integrated in parallel, respectively.In other words, part or all of capacitors 520C₁ and 520C₂ are configuredto be integrated.

The ADC logic is configured to convert outputs of the first or thesecond array module (520A or 520B) to a digital signal (OUTPUT shown inthe FIG. 5D.) When said ADC logic is performing conversion by said firstcapacitor array module while said integration circuit is performingintegration by said second capacitor array module. When said ADC logicis performing conversion by said second capacitor array module whilesaid integration circuit is performing integration by said firstcapacitor array module.

As shown in the FIG. 5G, said analog signal is selected from a pluralityof analog inputs and said digital signal is sent to a plurality ofdigital outputs. The plurality analog inputs are corresponding to saidplurality of digital outputs.

Please refer to FIG. 5D to 5G. In one embodiment of the presentinvention, an analog to digital converter (ADC) is provided. The ADC isconfigured to integrate a first input signal and a second input signal(1^(st) and 2^(nd) input signal shown in the FIG. 5G), respectively, andto convert in turn to a first n-bit digital signal and a second n-bitdigital signal (OUTPUT shown in the FIG. 5D.) The ADC comprises an inputsignal switch (550 shown in the FIG. 5G), a first capacitor array module(520A shown in the FIG. 5D, a second capacitor array module (520B shownin the FIG. 5D), an OP amplifier (510 shown in the FIG. 5D), acomparator (530 shown in the FIG. 5D), and a control logic (530 shown inthe FIG. 5D). The input signal switch is configured to receive saidfirst and said second input signals and to send out one of said inputsignals from an output end, which is further connected to the INPUTshown in the FIG. 5D. The first capacitor array module is configured tocouple said output end of said input signal switch and a referencevoltage VCM. The first capacitor array module comprises a plurality offirst capacitors (520C₁ shown in the FIG. 5E). The second capacitorarray module is configured to couple said output end of said inputsignal switch and said reference voltage VCM. The second capacitor arraymodule comprises a plurality of second capacitors (520C₂ shown in theFIG. 5E). The OP amplifier configured to couple said output end of saidinput signal switch and said reference voltage VCM. An output end ofsaid OP amplifier is configured to couple to said first and said secondcapacitor array modules. The first ends of said plurality of firstcapacitors are coupled to said output end of said input signal switch,said reference voltage VCM, or an output end of said comparator. Thefirst ends of said plurality of second capacitors are coupled to saidoutput end of said input signal switch, said reference voltage VCM, oran output end of said comparator. The control logic is configured toreceive an output signal of said comparator, to send out said n-bitdigital signals and a control signal (542, 544, 546, and 548,collectively shown in the FIG. 5E) to said first and said secondcapacitor array module.

The first capacitor array module further receives a first reset signalRST1. Second ends of said plurality of first capacitors coupled to afirst reset switch (switch 522A and switch b₁ shown in the FIG. 5E) inparallel which is connected to said reference voltage VCM. When saidfirst reset signal RST1 is a first signal, said first ends of saidplurality of first capacitors are coupled to said reference voltage VCMand said first reset switch is closed, whereas said first ends and saidsecond ends of said plurality of first capacitors are connected to saidreference voltage.

The second capacitor array module further receives a second reset signalRST2. Second ends of said plurality of second capacitors coupled to asecond reset switch (switch 522B and switch b₂ shown in the FIG. 5E) inparallel which is connected to said reference voltage VCM. When saidsecond reset signal RST2 is a first signal, said first ends of saidplurality of second capacitors are coupled to said reference voltage VCMand said first reset switch is closed, whereas said first ends and saidsecond ends of said plurality of second capacitors are connected to saidreference voltage.

The first capacitor array module further receives a first integrationsignal INT1. Second ends of said plurality of first capacitors coupledto a first integration switch (switch 524A and switch a₁ shown in theFIG. 5E) in parallel which is connected to said output end of said OPamplifier. When said first integration signal INT1 is a first signal,said first ends of said plurality of first capacitors are coupled inparallel to said output end of said input signal switch and said firstintegration switch is closed. The output signal of said input signalswitch is integrated by said plurality of first capacitors.

The second capacitor array module further receives a second integrationsignal INT2. Second ends of said plurality of second capacitors coupledto a second integration switch (switch 524B and switch a₂ shown in theFIG. 5E) in parallel which is connected to said output end of said OPamplifier. When said second integration signal INT1 is a first signal,said first ends of said plurality of second capacitors are coupled inparallel to said output end of said input signal switch and said secondintegration switch is closed. The output signal of said input signalswitch is integrated by said plurality of second capacitors.

The first capacitor array module further receives a first comparisonsignal CMP1. Second ends of said plurality of first capacitors coupledto a first comparison switch (switch c₁ shown in the FIG. 5E) and asecond comparison switch (switch d₁ shown in the FIG. 5E). The firstcomparison switch is connected to a first reference voltage VREFN andthe second comparison switch is connected to a second reference voltageVREFP. The first and said second comparison switch are controlled bysaid control signal. When said first comparison signal CMP1 is a firstsignal, said first ends of said plurality of first capacitors arecoupled in parallel to said input end of said comparator, said controllogic receives said output signal of said comparator and sends out saidn-bit digital signal and said control signal to said first capacitorarray module.

The second capacitor array module further receives a second comparisonsignal CMP2. Second ends of said plurality of second capacitors coupledto said first comparison switch (switch c₂ shown in the FIG. 5E) andsaid second comparison switch (switch d₂ shown in the FIG. 5E). Thefirst comparison switch is connected to said first reference voltageVREFN and the second comparison switch is connected to said secondreference voltage VREFP. The first and said second comparison switch arecontrolled by said control signal. When said second comparison signalCMP2 is a first signal, said first ends of said plurality of secondcapacitors are coupled in parallel to said input end of said comparator,said control logic receives said output signal of said comparator andsends out said n-bit digital signal and said control signal to saidfirst capacitor array module.

Capacity of said plurality of first capacitors and said plurality ofsecond capacitors is the same. The number of said plurality of firstcapacitors and the number of said plurality of second capacitors is n.The capacity ratio between said first capacitors is 2's multiple. Andthe capacity ratio between said second capacitors is 2's multiple.

Please refer to FIG. 5D to 5G and FIG. 7A to FIG. 7D. In anotherembodiment of the present invention, an operating method of an analog todigital converter (ADC) is provided. The ADC comprises an input signalswitch, a first and a second capacitor array modules, an OP amplifier, acomparator, and a control logic. The input signal switch is configuredto receive said first and said second input signals and to send out oneof said input signals from an output end. The first capacitor arraymodule is configured to couple said output end of said input signalswitch and a reference voltage VCM. The first capacitor array modulecomprises a plurality of first capacitors. The second capacitor arraymodule is configured to couple said output end of said input signalswitch and said reference voltage VCM. The second capacitor array modulecomprises a plurality of second capacitors. The OP amplifier isconfigured to couple said output end of said input signal switch andsaid reference voltage VCM. An output end of said OP amplifier isconfigured to couple to said first and said second capacitor arraymodules. First ends of said plurality of first capacitors are coupled tosaid output end of said input signal switch, said reference voltage VCM,or an output end of said comparator. First ends of said plurality ofsecond capacitors are coupled to said output end of said input signalswitch, said reference voltage VCM, or an output end of said comparator.The control logic is configured to receive an output signal of saidcomparator, to send out said n-bit digital signals and a control signalto said first and said second capacitor array module.

Please refer to FIG. 7A, the operating method comprises a step 710,performing steps for discharging said first capacitor array module asfollows: at step 711, coupling first ends of said plurality of firstcapacitors to said reference voltage VCM; and at step 712, couplingsecond ends of said plurality of first capacitors to said referencevoltage VCM.

Please refer to FIG. 7A, the operating method comprises a step 720performing steps for integration on said first input signal by saidfirst capacitor array module after the step 710, performing said stepsfor discharging said first capacitor array module as follows: at step721, outputting said first input signal by said input signal switch; atstep 722, coupling said first ends of said plurality of first capacitorsin parallel to said output end of said input signal switch; and at step723, coupling said second ends of said plurality of first capacitors inparallel to said input end of said OP amplifier.

Please refer to FIG. 7B, the operating method further comprises a step730, performing steps for conversion by said second capacitor arraymodule after the step 710, performing said steps for discharging saidfirst capacitor array module as follows: at step 731, coupling firstends of said plurality of second capacitors to said input end of saidcomparator; and at step 732, receiving said output signal of saidcomparator by the control logic and sending out said second n-bitdigital signal and said control signal to said second capacitor arraymodule.

Second ends of said plurality of second capacitors are coupled to afirst comparison switch and a second comparison switch. The firstcomparison switch is connected to a first reference voltage VREFN andthe second comparison switch is connected to a second reference voltageVREFP. The first and said second comparison switches are controlled bysaid control signal.

Please refer to FIG. 7B, the operating method further comprises a step740, performing steps for conversion by said first capacitor arraymodule after the step 720, performing said steps for integration by saidfirst capacitor array module as follows: at step 741, coupling saidfirst ends of said plurality of first capacitors to said input end ofsaid comparator; and at step 742, receiving said output signal of saidcomparator by the control logic and sending out said first n-bit digitalsignal and said control signal to said first capacitor array module.

Second ends of said plurality of first capacitors are coupled to a firstcomparison switch and a second comparison switch. The first comparisonswitch is connected to a first reference voltage VREFN and the secondcomparison switch is connected to a second reference voltage VREFP. Thefirst and said second comparison switches are controlled by said controlsignal.

Please refer to FIG. 7C, the operating method comprises a step 750,performing steps for discharging said second capacitor array moduleafter the step 730, performing steps for conversion by said secondcapacitor array module as follows: a step 751, coupling first ends ofsaid plurality of second capacitors to said reference voltage VCM; and astep 752, coupling second ends of said plurality of second capacitors tosaid reference voltage VCM.

Please refer to FIG. 7C, the operating method further comprises a step760, performing steps for integration by said second capacitor arraymodule after the step 750, performing steps for discharging said secondcapacitor array module as follows: at step 761, outputting said secondinput signal by said input signal switch; at step 762, coupling saidfirst ends of said plurality of second capacitors in parallel to saidoutput end of said input signal switch; and at step 763, coupling saidsecond ends of said plurality of second capacitors in parallel to saidinput end of said OP amplifier.

Please refer to FIG. 7B, the operating method further comprises the step710, steps for discharging said first capacitor array module after thestep 740, performing steps for conversion by said first capacitor arraymodule as follows: at step 711, coupling first ends of said plurality offirst capacitors to said reference voltage VCM; and at step 712,coupling second ends of said plurality of first capacitors to saidreference voltage VCM.

Time duration of sending said first n-bit digital signal is as the sameas time duration of sending said second n-bit digital signal. Capacityof said plurality of first capacitors and said plurality of secondcapacitors is the same, the number of said plurality of first capacitorsand the number of said plurality of second capacitors is n. The capacityratio between said first capacitors is 2's multiple, and the capacityratio between said second capacitors is 2's multiple.

Please refer to FIG. 7D, which is a timing sequence diagram of theoperating method in accordance with the present invention. The time axislies from left to right in the middle of the FIG. 7D. The stepsrepresented by arrows above the time axis are manipulated on the firstcapacitor array module. Similarly, the steps represented by arrows belowthe time axis are manipulated on the second capacitor array module. Inother words, steps 710, 720, and 740 are manipulated on the firstcapacitor array module; steps 730, 750, and 760 are manipulated on thesecond capacitor array module.

Ordinary skilled in the art can understand that the order of steps 710,720, and 740 can be repeated on the first capacitor array module; theorder of steps 730, 750, and 760 can be repeated on the second capacitormodule. Step 720 for integration is performed on the first capacitorarray module while step 730 for conversion is performed on the secondcapacitor array module. Step 740 for conversion is performed on thefirst capacitor array module while step 740 for integration is performedon the second capacitor array module. No matter the first or the secondcapacitor array module, steps 710 or 750 for discharging must beperformed after steps 740 or 730 for conversion.

Please refer to FIG. 8A, which shows an embodiment of the presentinvention, a circuit for concurrent integration of multiple differentialsignals is provided. The circuit comprises a plurality of Stage 1integration (sample and hold) circuit 810A, 810B, and 810C arranged inarray. Although three circuit are shown in the FIG. 8A, ordinary skilledin the art can understand that the number of circuit 810 can be morethan 3.

Each of Stage 1 integration circuit 810 integrates an input signal, asfirst, second, and third input signals in the FIG. 8A and outputsconcurrently a positive sampling signal and a negative sampling signal.Take the circuit 810A as an example, it is configured to integrate thefirst input signal and concurrently to output a first positive and afirst negative sampling signals, or so-called Stage 1 positive signaland Stage 1 negative signal. Both signals are generated concurrently,there is no any time delay caused by converter.

Each of said Stage 2 integration circuit 820 is configured to integratea differential signal from a Stage 1 positive signal sent from acorresponding Stage 1 integration circuit 810 and a Stage 1 negativesignal sent from another Stage 1 integration circuit 810 next to saidcorresponding Stage 1 integration circuit 810 to output a Stage 2signal. Take the first State 2 integration circuit 820A as an example,the first Stage 2 input signal is a differential signal combined fromthe first positive signal of the first Stage 1 integration circuit 810Aand the second negative signal of the second Stage 1 integration circuit810B which is next to the circuit 810A.

In one embodiment, the differential signal is combined prior to beingsent to the Stage 2 integration circuit 820. In another embodiment, theStage 2 integration circuit 820 receives and combine said Stage 1positive and negative signals into said differential signal.

As shown in the FIG. 8A, a plurality of analog to digital converters 830arranged in array are included. Each of analog to digital converter 830converts a Stage 2 signal from a corresponding Stage 2 integrationcircuit 820 to a digital signal. At least one of said plurality ofanalog to digital converters 830 and corresponding Stage 2 integrationcircuit 820 is a first successive approximation register analog todigital converter (SAR-ADC) as shown in the FIG. 5A to 5C. In otherembodiment, the analog to digital converters 830 and corresponding Stage2 integration circuit 820 is a second successive approximation registeranalog to digital converter (SAR-ADC) as shown in the FIG. 5D to 5G.

Please refer to FIG. 8A, which shows a sensor circuit module inaccordance with an embodiment of the present invention. The modulecomprises a 1^(st) Stage 1 S/H circuit 810A, a 2^(nd) Stage 1 S/Hcircuit 810B, and a 1^(st) Stage 2 S/H circuit 820A. The first Stage 1sample and hold (S/H) circuit 810A is configured to integrate a firstinput signal and to send out a first positive signal and a firstnegative signal. Said first positive signal is reverse to said firstnegative signal. The second Stage 1 S/H circuit 810B is configured tointegrate a second input signal and to send out a second positive signaland a second negative signal. Second positive signal is reverse to saidsecond negative signal. The first Stage 2 S/H circuit 820A is configuredto receive and combine said first positive signal and said secondnegative signal into a first Stage 2 input signal to be integrated bysaid first Stage 2 S/H circuit 820A.

The sensor circuit module further comprises a 3^(rd) Stage 1 S/H circuit810C and a 2^(nd) Stage 2 S/H 820B. The third Stage 1 S/H circuit 810Cis configured to integrate a third input signal and to send out a thirdpositive signal and third negative signal. Said third positive signal isreverse to said third negative signal. The second Stage 2 S/H circuit820B is configured to receive and combine said second positive signaland said third negative signal into a second Stage 2 input signal to beintegrated by said second Stage 2 S/H circuit 820B.

The sensor circuit module further comprises a third Stage 2 S/H circuit820C configured to receive and combine said third positive signal andsaid first negative signal into a third Stage 2 input signal to beintegrated by said third Stage 2 S/H circuit 820C.

The sensor circuit module further comprises a first analog to digitalconverter 830A configured to convert an analog output signal from saidfirst Stage 2 S/H circuit 820A to a first digital signal.

In one embodiment, the first Stage 2 input signal is combined from saidfirst positive (sampling) signal and said second negative (sampling)signal prior to said first Stage 2 S/H circuit 820A receives said firstStage 2 input signal. In another embodiment, the first Stage 2 S/Hcircuit 820A receives said first positive (sampling) signal and saidsecond negative (sampling) signal prior to combine and integrate to saidfirst Stage 2 input signal.

Please refer to FIG. 8B, which illustrates another embodiment of thepresent invention. The first Stage 2 S/H circuit 820A and said firstanalog to digital converter 830A is a first successive approximationregister analog to digital converter (SAR-ADC) 840A. The said firstpositive (sampling) signal and said first negative (sampling) signal aresent concurrently, there is no any time delay caused by inverterin-between. Please refer to FIG. 5A to 5C, ordinary skilled in the artcan understand the implementations of the SAR-ADC 840A.

The SAR-ADC 840A is configured to integrate said first Stage 2 inputsignal and to convert it to a first n-bit digital signal. The SAR-ADC840A comprises a capacitor array module, an OP amplifier, a comparator,and a control logic. The capacitor array module is configured to receivean input signal and a reference voltage VCM. The capacitor array modulecomprises a plurality of capacitors. First ends of said plurality ofcapacitors are coupled to said input signal, said reference voltage VCM,or an input end of said comparator. An output end of said comparator iscoupled to said capacitor array module. The said control logicconfigured to receive an output end of said comparator and send out ann-bit digital signal and a control signal to said capacitor arraymodule.

Please refer to FIG. 8C, which sketches an embodiment of the presentinvention. The first Stage 2 S/H circuit 820A, the second Stage 2 S/Hcircuit 820B, and analog to digital conversion circuit which convertsoutputs of the first and the second Stage 2 S/H circuit 820A and 820B isa second SAR-ADC. Please refer to FIG. 5D and FIG. 5G, ordinary skilledin the art can understand the implementations of second SAR-ADC 850A.

The SAR-ADC 850A comprises an input signal switch, a first and a secondcapacitor array modules, an OP amplifier, a comparator, and a controllogic. The input signal switch is configured to receive said first andsaid second input signals and to send out one of said input signals froman output end. The first capacitor array module is configured to couplesaid output end of said input signal switch and a reference voltage VCM.The first capacitor array module comprises a plurality of firstcapacitors. The second capacitor array module is configured to couplesaid output end of said input signal switch and said reference voltageVCM. The second capacitor array module comprises a plurality of secondcapacitors. The OP amplifier is configured to couple said output end ofsaid input signal switch and said reference voltage VCM. An output endof said OP amplifier is configured to couple to said first and saidsecond capacitor array modules. First ends of said plurality of firstcapacitors are coupled to said output end of said input signal switch,said reference voltage VCM, or an output end of said comparator. Firstends of said plurality of second capacitors are coupled to said outputend of said input signal switch, said reference voltage VCM, or anoutput end of said comparator. The control logic is configured toreceive an output signal of said comparator, to send out said n-bitdigital signals and a control signal to said first and said secondcapacitor array module.

The first input signal and the second input signal coupled to a firstwire and a second wire of a touch sensor module, respectively. The firstwire is next to the second wire.

Please refer to FIG. 8A to 8C and 9A, which shows an operating method ofa sensor circuit module in accordance with an embodiment of the presentinvention. At step 902, receiving a first positive signal from a firstStage 1 S/H circuit. The first positive signal is reverse to a firstnegative signal from the first Stage 1 S/H circuit. At step 904,receiving a second negative signal from a second Stage 1 S/H circuit.The second negative signal is reverse to a second positive signal fromthe second Stage 1 S/H circuit. At step 906, receiving and combiningsaid first positive signal and said second negative signal to a firstStage 2 input signal. And at step 908, integrating said first Stage 2input signal.

Please refer to FIG. 9B, the operating method shown in the FIG. 9A couldfurther comprises the followings. At step 910, receiving said secondpositive signal from said second Stage 1 S/H circuit. At step 912,receiving a third negative signal from a third Stage 1 S/H circuit. Thethird negative signal is reverse to a third positive signal from saidthird Stage 1 S/H circuit. At step 914, receiving and combining saidsecond positive signal and said third negative signal to a second Stage2 input signal. At step 916, integrating said second Stage 2 inputsignal.

Please refer to FIG. 9C, the operating method shown in the FIGS. 9A and9B could further comprises the followings. At step 918, receiving saidfirst negative signal from said first Stage 1 S/H circuit. At step 920,receiving said third positive signal from said third Stage 1 S/Hcircuit. At step 922, receiving and combing said first negative signaland said third positive signal to a third Stage 2 input signal. And atstep 924, integrating said third Stage 2 input signal.

Ordinary skilled in the art can understand the steps shown in the FIGS.9A, 9B, and 9B can be performed independently and/or concurrently.

The operating method further comprises conversion on the integratedStage 2 input signal to a digital signal by a first SAR-ADC. The SAR-ADCis configured to integrate said Stage 2 input signal and to convert itto a first n-bit digital signal. The SAR-ADC comprises a capacitor arraymodule, an OP amplifier, a comparator, and a control logic. Thecapacitor array module is configured to receive an input signal and areference voltage VCM. The capacitor array module comprises a pluralityof capacitors. First ends of said plurality of capacitors are coupled tosaid input signal, said reference voltage VCM, or an input end of saidcomparator. An output end of said comparator is coupled to saidcapacitor array module. The said control logic configured to receive anoutput end of said comparator and send out an n-bit digital signal and acontrol signal to said capacitor array module.

The operating method may further comprises: converting said first Stage2 input signal to a first digital signal; and converting said secondStage 2 input signal to a second digital signal. Both the convertingsteps are performed by a second SAR-ADC.

The SAR-ADC comprises an input signal switch, a first and a secondcapacitor array modules, an OP amplifier, a comparator, and a controllogic. The input signal switch is configured to receive said first andsaid second input signals and to send out one of said input signals froman output end. The first capacitor array module is configured to couplesaid output end of said input signal switch and a reference voltage VCM.The first capacitor array module comprises a plurality of firstcapacitors. The second capacitor array module is configured to couplesaid output end of said input signal switch and said reference voltageVCM. The second capacitor array module comprises a plurality of secondcapacitors. The OP amplifier is configured to couple said output end ofsaid input signal switch and said reference voltage VCM. An output endof said OP amplifier is configured to couple to said first and saidsecond capacitor array modules. First ends of said plurality of firstcapacitors are coupled to said output end of said input signal switch,said reference voltage VCM, or an output end of said comparator. Firstends of said plurality of second capacitors are coupled to said outputend of said input signal switch, said reference voltage VCM, or anoutput end of said comparator. The control logic is configured toreceive an output signal of said comparator, to send out said n-bitdigital signals and a control signal to said first and said secondcapacitor array module.

The first input signal and the second input signal coupled to a firstwire and a second wire of a touch sensor module, respectively. The firstwire is next to the second wire.

The above embodiments are only used to illustrate the principles of thepresent invention, and they should not be construed as to limit thepresent invention in any way. The above embodiments can be modified bythose with ordinary skill in the art without departing from the scope ofthe present invention as defined in the following appended claims.

1. A circuit for concurrent integration of multiple differentialsignals, comprises: a plurality of Stage 1 integration circuit arrangedin array, wherein each of said Stage 1 integration circuit is configuredto concurrently integrate an input signal to send out a Stage 1 positivesignal and a Stage 1 negative signal which is reverse to said Stage 1positive signal; and a plurality of Stage 2 integration circuit arrangedin array, wherein each of said Stage 2 integration circuit is configuredto integrate a differential signal from a Stage 1 positive signal sentfrom a corresponding Stage 1 integration circuit and a Stage 1 negativesignal sent from another Stage 1 integration circuit next to saidcorresponding Stage 1 integration circuit to output a Stage 2 signal. 2.The circuit of claim 1, further comprises: a plurality of analog todigital converters arranged in array, wherein each of analog to digitalconverter converts a Stage 2 signal from a corresponding Stage 2integration circuit to a digital signal.
 3. The circuit of claim 2,wherein at least one of said plurality of analog to digital convertersand corresponding Stage 2 integration circuit is a first successiveapproximation register analog to digital converter (SAR-ADC).
 4. Thecircuit of claim 3, wherein said first SAR-ADC comprises: a capacitorarray module having a plurality of capacitors; a integration circuitconfigured to integrate an analog signal by said capacitor array module;and an analog to digital conversion (ADC) logic configured to convertthe output of said capacitor array module to a digital signal.
 5. Thecircuit of claim 1, wherein said Stage 1 positive and negative signalsare sent concurrently, there is no any time delay caused by inverterin-between.
 6. The circuit of claim 1, wherein said differential signalis combined prior to being sent to said Stage 2 integration circuit. 7.The circuit of claim 1, wherein said Stage 2 integration circuitreceives and combine said Stage 1 positive and negative signals intosaid differential signal.
 8. The circuit of claim 2, wherein at leastpart of said plurality of analog to digital converters and correspondingStage 2 integration circuit is a second successive approximationregister analog to digital converter (SAR-ADC), wherein said secondSAR-ADC comprises: a first capacitor array module having a plurality ofcapacitors; a second capacitor array module having a plurality ofcapacitors; a integration circuit configured to integrate an analogsignal by said first or said second capacitor array module; and ananalog to digital conversion (ADC) logic configured to convert theoutput of said first or said second capacitor array module to a digitalsignal, wherein said ADC logic performing conversion by said firstcapacitor array module while said integration circuit performingintegration by said second capacitor array module, and said ADC logicperforming conversion by said second capacitor array module while saidintegration circuit performing integration by said first capacitor arraymodule.
 9. A sensor circuit module, comprises: a first Stage 1 sampleand hold (S/H) circuit configured to integrate a first input signal andto send out a first positive signal and a first negative signal, whereinsaid first positive signal is reverse to said first negative signal; asecond Stage 1 S/H circuit configured to integrate a second input signaland to send out a second positive signal and a second negative signal,wherein said second positive signal is reverse to said second negativesignal; and a first Stage 2 S/H circuit configured to receive andcombine said first positive signal and said second negative signal intoa first Stage 2 input signal to be integrated by said first Stage 2 S/Hcircuit.
 10. The sensor circuit module of claim 9, comprises: a thirdStage 1 S/H circuit configured to integrate a third input signal and tosend out a third positive signal and third negative signal, wherein saidthird positive signal is reverse to said third negative signal; and asecond Stage 2 S/H circuit configured to receive and combine said secondpositive signal and said third negative signal into a second Stage 2input signal to be integrated by said second Stage 2 S/H circuit. 11.The sensor circuit module of claim 10, comprises: a third Stage 2 S/Hcircuit configured to receive and combine said third positive signal andsaid first negative signal into a third Stage 2 input signal to beintegrated by said third Stage 2 S/H circuit.
 12. The sensor circuitmodule of claim 9, comprises: a first analog to digital converterconfigured to convert an analog output signal from said first Stage 2S/H circuit to a first digital signal.
 13. The sensor circuit module ofclaim 12, wherein said first Stage 2 S/H circuit and said first analogto digital converter is a first successive approximation register analogto digital converter (SAR-ADC), wherein said first positive signal andsaid first negative signal are sent concurrently, there is no any timedelay caused by inverter in-between.
 14. The sensor circuit module ofclaim 13, wherein said first SAR-ADC configured to integrate said firstStage 2 input signal and to convert to a first digital signal, saidSAR-ADC comprises: a capacitor array module having a plurality ofcapacitors; an integration circuit configured to integrate an analogsignal by said capacitor array module; and an analog to digitalconversion (ADC) logic configured to convert the output of saidcapacitor array module to a digital signal.
 15. The sensor circuitmodule of claim 10, wherein said first Stage 2 S/H circuit, said secondStage 2 S/H circuit, and analog to digital converter corresponding tosaid first and second Stage 2 S/H circuit is a second SAR-ADC.
 16. Thesensor circuit module of claim 15, wherein said second SAR-ADCconfigured to integrate, in turn, said first and said second Stage 2input signals, respectively, and to convert to corresponding a firstn-bit digital signal and a second n-bit digital signal, said secondSAR-ADC comprises: a first capacitor array module having a plurality ofcapacitors; a second capacitor array module having a plurality ofcapacitors; a integration circuit configured to integrate an analogsignal by said first or said second capacitor array module; and ananalog to digital conversion (ADC) logic configured to convert theoutput of said first or said second capacitor array module to a digitalsignal, wherein said ADC logic performing conversion by said firstcapacitor array module while said integration circuit performingintegration by said second capacitor array module, and said ADC logicperforming conversion by said second capacitor array module while saidintegration circuit performing integration by said first capacitor arraymodule.
 17. The sensor circuit module of claim 9, wherein said firstinput signal and said second input signal coupled to a first wire and asecond wire of a touch sensor module, respectively, wherein said firstwire is next to said second wire.
 18. The sensor circuit module of claim9, wherein said first Stage 2 input signal is combined from said firstpositive signal and said second negative signal prior to said firstStage 2 S/H circuit receives said first Stage 2 input signal.
 19. Thesensor circuit module of claim 9, wherein said first Stage 2 S/H circuitreceives said first positive signal and said second negative signalprior to combine and integrate to said first Stage 2 input signal. 20.An operating method of a sensor circuit module, comprises: receiving afirst positive signal from a first Stage 1 S/H circuit, wherein saidfirst positive signal is reverse to a first negative signal from saidfirst Stage 1 S/H circuit; receiving a second negative signal from asecond Stage 1 S/H circuit, wherein said second negative signal isreverse to a second positive signal from said second Stage 1 S/Hcircuit; receiving and combining said first positive signal and saidsecond negative signal to a first Stage 2 input signal; and integratingsaid first Stage 2 input signal.
 21. The operating method of claim 20,further comprises: receiving said second positive signal from saidsecond Stage 1 S/H circuit; receiving a third negative signal from athird Stage 1 S/H circuit, wherein said third negative signal is reverseto a third positive signal from said third Stage 1 S/H circuit;receiving and combining said second positive signal and said thirdnegative signal to a second Stage 2 input signal; and integrating saidsecond Stage 2 input signal.
 22. The operating method of claim 21,further comprises: receiving said first negative signal from said firstStage 1 S/H circuit; receiving said third positive signal from saidthird Stage 1 S/H circuit; receiving and combing said first negativesignal and said third positive signal to a third Stage 2 input signal;and integrating said third Stage 2 input signal.
 23. The operatingmethod of claim 20, further comprises converting an integrated from saidfirst Stage 2 input signal to a first digital signal.
 24. The operatingmethod of claim 23, wherein said converting step is performed by a firstsuccessive approximation register analog to digital converter (SAR-ADC),wherein said first positive signal and said first negative signal aresent concurrently, there is no any time delay caused by inverterin-between.
 25. The operating method of claim 24, wherein said SAR-ADCconfigured to integrate said first Stage 2 input signal and to convertto said first digital signal, said SAR-ADC comprises: a capacitor arraymodule having a plurality of capacitors; a integration circuitconfigured to integrate an analog signal by said capacitor array module;and an analog to digital conversion (ADC) logic configured to convertthe output of said capacitor array module to a digital signal.
 26. Theoperating method of claim 21, further comprises: converting said firstStage 2 input signal to a first digital signal; and converting saidsecond Stage 2 input signal to a second digital signal, wherein saidconverting steps are performed by a second SAR-ADC.
 27. The operatingmethod of claim 26, wherein second SAR-ADC configured to integrate, inturn, said first and said second Stage 2 input signals, respectively,and to convert to corresponding a first n-bit digital signal and asecond n-bit digital signal, said second SAR-ADC comprises: a firstcapacitor array module having a plurality of capacitors; a secondcapacitor array module having a plurality of capacitors; a integrationcircuit configured to integrate an analog signal by said first or saidsecond capacitor array module; and an analog to digital conversion (ADC)logic configured to convert the output of said first or said secondcapacitor array module to a digital signal, wherein said ADC logicperforming conversion by said first capacitor array module while saidintegration circuit performing integration by said second capacitorarray module, and said ADC logic performing conversion by said secondcapacitor array module while said integration circuit performingintegration by said first capacitor array module.
 28. The operatingmethod of claim 20, wherein said first input signal and said secondinput signal coupled to a first wire and a second wire of a touch sensormodule, respectively, wherein said first wire is next to said secondwire.
 29. The operating method of claim 20, wherein said receiving andcombining step is performed as follows: combining said first positivesignal and said second negative signal to said first Stage 2 inputsignal prior to receiving said first Stage input signal by a first Stage2 S/H circuit.
 30. The operating method of claim 20, wherein saidreceiving and combining step is performed as follows: receiving aidfirst positive signal and said second negative signal by a first Stage 2S/H circuit prior to combining them to said first Stage 2 input signal.